1957 lines
48 KiB
C
1957 lines
48 KiB
C
#pragma once
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#ifndef CPUINFO_H
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#define CPUINFO_H
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#ifndef __cplusplus
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#include <stdbool.h>
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#endif
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#ifdef __APPLE__
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#include <TargetConditionals.h>
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#endif
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#include <stdint.h>
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/* Identify architecture and define corresponding macro */
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#if defined(__i386__) || defined(__i486__) || defined(__i586__) || defined(__i686__) || defined(_M_IX86)
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#define CPUINFO_ARCH_X86 1
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#endif
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#if defined(__x86_64__) || defined(__x86_64) || defined(_M_X64) || defined(_M_AMD64)
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#define CPUINFO_ARCH_X86_64 1
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#endif
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#if defined(__arm__) || defined(_M_ARM)
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#define CPUINFO_ARCH_ARM 1
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#endif
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#if defined(__aarch64__) || defined(_M_ARM64)
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#define CPUINFO_ARCH_ARM64 1
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#endif
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#if defined(__PPC64__) || defined(__powerpc64__) || defined(_ARCH_PPC64)
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#define CPUINFO_ARCH_PPC64 1
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#endif
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#if defined(__asmjs__)
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#define CPUINFO_ARCH_ASMJS 1
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#endif
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#if defined(__wasm__)
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#if defined(__wasm_simd128__)
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#define CPUINFO_ARCH_WASMSIMD 1
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#else
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#define CPUINFO_ARCH_WASM 1
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#endif
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#endif
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/* Define other architecture-specific macros as 0 */
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#ifndef CPUINFO_ARCH_X86
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#define CPUINFO_ARCH_X86 0
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#endif
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#ifndef CPUINFO_ARCH_X86_64
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#define CPUINFO_ARCH_X86_64 0
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#endif
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#ifndef CPUINFO_ARCH_ARM
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#define CPUINFO_ARCH_ARM 0
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#endif
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#ifndef CPUINFO_ARCH_ARM64
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#define CPUINFO_ARCH_ARM64 0
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#endif
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#ifndef CPUINFO_ARCH_PPC64
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#define CPUINFO_ARCH_PPC64 0
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#endif
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#ifndef CPUINFO_ARCH_ASMJS
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#define CPUINFO_ARCH_ASMJS 0
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#endif
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#ifndef CPUINFO_ARCH_WASM
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#define CPUINFO_ARCH_WASM 0
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#endif
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#ifndef CPUINFO_ARCH_WASMSIMD
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#define CPUINFO_ARCH_WASMSIMD 0
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#endif
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#if CPUINFO_ARCH_X86 && defined(_MSC_VER)
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#define CPUINFO_ABI __cdecl
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#elif CPUINFO_ARCH_X86 && defined(__GNUC__)
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#define CPUINFO_ABI __attribute__((__cdecl__))
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#else
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#define CPUINFO_ABI
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#endif
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#define CPUINFO_CACHE_UNIFIED 0x00000001
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#define CPUINFO_CACHE_INCLUSIVE 0x00000002
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#define CPUINFO_CACHE_COMPLEX_INDEXING 0x00000004
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struct cpuinfo_cache {
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/** Cache size in bytes */
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uint32_t size;
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/** Number of ways of associativity */
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uint32_t associativity;
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/** Number of sets */
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uint32_t sets;
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/** Number of partitions */
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uint32_t partitions;
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/** Line size in bytes */
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uint32_t line_size;
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/**
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* Binary characteristics of the cache (unified cache, inclusive cache, cache with complex indexing).
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*
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* @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE, CPUINFO_CACHE_COMPLEX_INDEXING
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*/
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uint32_t flags;
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/** Index of the first logical processor that shares this cache */
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uint32_t processor_start;
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/** Number of logical processors that share this cache */
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uint32_t processor_count;
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};
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struct cpuinfo_trace_cache {
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uint32_t uops;
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uint32_t associativity;
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};
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#define CPUINFO_PAGE_SIZE_4KB 0x1000
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#define CPUINFO_PAGE_SIZE_1MB 0x100000
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#define CPUINFO_PAGE_SIZE_2MB 0x200000
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#define CPUINFO_PAGE_SIZE_4MB 0x400000
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#define CPUINFO_PAGE_SIZE_16MB 0x1000000
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#define CPUINFO_PAGE_SIZE_1GB 0x40000000
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struct cpuinfo_tlb {
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uint32_t entries;
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uint32_t associativity;
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uint64_t pages;
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};
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/** Vendor of processor core design */
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enum cpuinfo_vendor {
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/** Processor vendor is not known to the library, or the library failed to get vendor information from the OS. */
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cpuinfo_vendor_unknown = 0,
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/* Active vendors of modern CPUs */
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/**
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* Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor microarchitectures.
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*
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* Sold its ARM design subsidiary in 2006. The last ARM processor design was released in 2004.
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*/
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cpuinfo_vendor_intel = 1,
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/** Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor microarchitectures. */
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cpuinfo_vendor_amd = 2,
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/** ARM Holdings plc. Vendor of ARM and ARM64 processor microarchitectures. */
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cpuinfo_vendor_arm = 3,
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/** Qualcomm Incorporated. Vendor of ARM and ARM64 processor microarchitectures. */
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cpuinfo_vendor_qualcomm = 4,
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/** Apple Inc. Vendor of ARM and ARM64 processor microarchitectures. */
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cpuinfo_vendor_apple = 5,
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/** Samsung Electronics Co., Ltd. Vendir if ARM64 processor microarchitectures. */
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cpuinfo_vendor_samsung = 6,
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/** Nvidia Corporation. Vendor of ARM64-compatible processor microarchitectures. */
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cpuinfo_vendor_nvidia = 7,
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/** MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures. */
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cpuinfo_vendor_mips = 8,
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/** International Business Machines Corporation. Vendor of PowerPC processor microarchitectures. */
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cpuinfo_vendor_ibm = 9,
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/** Ingenic Semiconductor. Vendor of MIPS processor microarchitectures. */
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cpuinfo_vendor_ingenic = 10,
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/**
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* VIA Technologies, Inc. Vendor of x86 and x86-64 processor microarchitectures.
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*
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* Processors are designed by Centaur Technology, a subsidiary of VIA Technologies.
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*/
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cpuinfo_vendor_via = 11,
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/** Cavium, Inc. Vendor of ARM64 processor microarchitectures. */
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cpuinfo_vendor_cavium = 12,
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/** Broadcom, Inc. Vendor of ARM processor microarchitectures. */
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cpuinfo_vendor_broadcom = 13,
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/** Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor microarchitectures. */
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cpuinfo_vendor_apm = 14,
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/**
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* Huawei Technologies Co., Ltd. Vendor of ARM64 processor microarchitectures.
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*
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* Processors are designed by HiSilicon, a subsidiary of Huawei.
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*/
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cpuinfo_vendor_huawei = 15,
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/**
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* Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor of x86-64 processor microarchitectures.
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*
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* Processors are variants of AMD cores.
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*/
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cpuinfo_vendor_hygon = 16,
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/* Active vendors of embedded CPUs */
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/** Texas Instruments Inc. Vendor of ARM processor microarchitectures. */
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cpuinfo_vendor_texas_instruments = 30,
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/** Marvell Technology Group Ltd. Vendor of ARM processor microarchitectures. */
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cpuinfo_vendor_marvell = 31,
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/** RDC Semiconductor Co., Ltd. Vendor of x86 processor microarchitectures. */
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cpuinfo_vendor_rdc = 32,
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/** DM&P Electronics Inc. Vendor of x86 processor microarchitectures. */
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cpuinfo_vendor_dmp = 33,
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/** Motorola, Inc. Vendor of PowerPC and ARM processor microarchitectures. */
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cpuinfo_vendor_motorola = 34,
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/* Defunct CPU vendors */
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/**
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* Transmeta Corporation. Vendor of x86 processor microarchitectures.
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*
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* Now defunct. The last processor design was released in 2004.
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* Transmeta processors implemented VLIW ISA and used binary translation to execute x86 code.
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*/
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cpuinfo_vendor_transmeta = 50,
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/**
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* Cyrix Corporation. Vendor of x86 processor microarchitectures.
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*
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* Now defunct. The last processor design was released in 1996.
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*/
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cpuinfo_vendor_cyrix = 51,
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/**
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* Rise Technology. Vendor of x86 processor microarchitectures.
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*
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* Now defunct. The last processor design was released in 1999.
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*/
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cpuinfo_vendor_rise = 52,
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/**
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* National Semiconductor. Vendor of x86 processor microarchitectures.
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*
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* Sold its x86 design subsidiary in 1999. The last processor design was released in 1998.
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*/
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cpuinfo_vendor_nsc = 53,
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/**
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* Silicon Integrated Systems. Vendor of x86 processor microarchitectures.
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*
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* Sold its x86 design subsidiary in 2001. The last processor design was released in 2001.
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*/
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cpuinfo_vendor_sis = 54,
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/**
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* NexGen. Vendor of x86 processor microarchitectures.
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*
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* Now defunct. The last processor design was released in 1994.
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* NexGen designed the first x86 microarchitecture which decomposed x86 instructions into simple microoperations.
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*/
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cpuinfo_vendor_nexgen = 55,
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/**
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* United Microelectronics Corporation. Vendor of x86 processor microarchitectures.
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*
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* Ceased x86 in the early 1990s. The last processor design was released in 1991.
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* Designed U5C and U5D processors. Both are 486 level.
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*/
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cpuinfo_vendor_umc = 56,
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/**
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* Digital Equipment Corporation. Vendor of ARM processor microarchitecture.
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*
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* Sold its ARM designs in 1997. The last processor design was released in 1997.
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*/
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cpuinfo_vendor_dec = 57,
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};
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/**
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* Processor microarchitecture
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*
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* Processors with different microarchitectures often have different instruction performance characteristics,
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* and may have dramatically different pipeline organization.
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*/
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enum cpuinfo_uarch {
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/** Microarchitecture is unknown, or the library failed to get information about the microarchitecture from OS */
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cpuinfo_uarch_unknown = 0,
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/** Pentium and Pentium MMX microarchitecture. */
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cpuinfo_uarch_p5 = 0x00100100,
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/** Intel Quark microarchitecture. */
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cpuinfo_uarch_quark = 0x00100101,
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/** Pentium Pro, Pentium II, and Pentium III. */
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cpuinfo_uarch_p6 = 0x00100200,
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/** Pentium M. */
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cpuinfo_uarch_dothan = 0x00100201,
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/** Intel Core microarchitecture. */
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cpuinfo_uarch_yonah = 0x00100202,
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/** Intel Core 2 microarchitecture on 65 nm process. */
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cpuinfo_uarch_conroe = 0x00100203,
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/** Intel Core 2 microarchitecture on 45 nm process. */
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cpuinfo_uarch_penryn = 0x00100204,
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/** Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st gen). */
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cpuinfo_uarch_nehalem = 0x00100205,
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/** Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen). */
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cpuinfo_uarch_sandy_bridge = 0x00100206,
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/** Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen). */
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cpuinfo_uarch_ivy_bridge = 0x00100207,
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/** Intel Haswell microarchitecture (Core i3/i5/i7 4th gen). */
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cpuinfo_uarch_haswell = 0x00100208,
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/** Intel Broadwell microarchitecture. */
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cpuinfo_uarch_broadwell = 0x00100209,
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/** Intel Sky Lake microarchitecture (14 nm, including Kaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake). */
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cpuinfo_uarch_sky_lake = 0x0010020A,
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/** DEPRECATED (Intel Kaby Lake microarchitecture). */
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cpuinfo_uarch_kaby_lake = 0x0010020A,
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/** Intel Palm Cove microarchitecture (10 nm, Cannon Lake). */
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cpuinfo_uarch_palm_cove = 0x0010020B,
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/** Intel Sunny Cove microarchitecture (10 nm, Ice Lake). */
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cpuinfo_uarch_sunny_cove = 0x0010020C,
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/** Pentium 4 with Willamette, Northwood, or Foster cores. */
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cpuinfo_uarch_willamette = 0x00100300,
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/** Pentium 4 with Prescott and later cores. */
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cpuinfo_uarch_prescott = 0x00100301,
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/** Intel Atom on 45 nm process. */
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cpuinfo_uarch_bonnell = 0x00100400,
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/** Intel Atom on 32 nm process. */
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cpuinfo_uarch_saltwell = 0x00100401,
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/** Intel Silvermont microarchitecture (22 nm out-of-order Atom). */
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cpuinfo_uarch_silvermont = 0x00100402,
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/** Intel Airmont microarchitecture (14 nm out-of-order Atom). */
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cpuinfo_uarch_airmont = 0x00100403,
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/** Intel Goldmont microarchitecture (Denverton, Apollo Lake). */
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cpuinfo_uarch_goldmont = 0x00100404,
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/** Intel Goldmont Plus microarchitecture (Gemini Lake). */
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cpuinfo_uarch_goldmont_plus = 0x00100405,
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/** Intel Knights Ferry HPC boards. */
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cpuinfo_uarch_knights_ferry = 0x00100500,
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/** Intel Knights Corner HPC boards (aka Xeon Phi). */
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cpuinfo_uarch_knights_corner = 0x00100501,
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/** Intel Knights Landing microarchitecture (second-gen MIC). */
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cpuinfo_uarch_knights_landing = 0x00100502,
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/** Intel Knights Hill microarchitecture (third-gen MIC). */
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cpuinfo_uarch_knights_hill = 0x00100503,
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/** Intel Knights Mill Xeon Phi. */
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cpuinfo_uarch_knights_mill = 0x00100504,
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/** Intel/Marvell XScale series. */
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cpuinfo_uarch_xscale = 0x00100600,
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/** AMD K5. */
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cpuinfo_uarch_k5 = 0x00200100,
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/** AMD K6 and alike. */
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cpuinfo_uarch_k6 = 0x00200101,
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/** AMD Athlon and Duron. */
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cpuinfo_uarch_k7 = 0x00200102,
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/** AMD Athlon 64, Opteron 64. */
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cpuinfo_uarch_k8 = 0x00200103,
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/** AMD Family 10h (Barcelona, Istambul, Magny-Cours). */
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cpuinfo_uarch_k10 = 0x00200104,
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/**
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* AMD Bulldozer microarchitecture
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* Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs.
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*/
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cpuinfo_uarch_bulldozer = 0x00200105,
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/**
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* AMD Piledriver microarchitecture
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* Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu Dhabi Opteron CPUs.
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*/
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cpuinfo_uarch_piledriver = 0x00200106,
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/** AMD Steamroller microarchitecture (Kaveri APUs). */
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cpuinfo_uarch_steamroller = 0x00200107,
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/** AMD Excavator microarchitecture (Carizzo APUs). */
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cpuinfo_uarch_excavator = 0x00200108,
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/** AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs). */
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cpuinfo_uarch_zen = 0x00200109,
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/** AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs). */
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cpuinfo_uarch_zen2 = 0x0020010A,
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/** AMD Zen 3 microarchitecture. */
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cpuinfo_uarch_zen3 = 0x0020010B,
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/** AMD Zen 4 microarchitecture. */
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cpuinfo_uarch_zen4 = 0x0020010C,
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/** NSC Geode and AMD Geode GX and LX. */
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cpuinfo_uarch_geode = 0x00200200,
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/** AMD Bobcat mobile microarchitecture. */
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cpuinfo_uarch_bobcat = 0x00200201,
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/** AMD Jaguar mobile microarchitecture. */
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cpuinfo_uarch_jaguar = 0x00200202,
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/** AMD Puma mobile microarchitecture. */
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cpuinfo_uarch_puma = 0x00200203,
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/** ARM7 series. */
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cpuinfo_uarch_arm7 = 0x00300100,
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/** ARM9 series. */
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cpuinfo_uarch_arm9 = 0x00300101,
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/** ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore. */
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cpuinfo_uarch_arm11 = 0x00300102,
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/** ARM Cortex-A5. */
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cpuinfo_uarch_cortex_a5 = 0x00300205,
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/** ARM Cortex-A7. */
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cpuinfo_uarch_cortex_a7 = 0x00300207,
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/** ARM Cortex-A8. */
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cpuinfo_uarch_cortex_a8 = 0x00300208,
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/** ARM Cortex-A9. */
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cpuinfo_uarch_cortex_a9 = 0x00300209,
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/** ARM Cortex-A12. */
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cpuinfo_uarch_cortex_a12 = 0x00300212,
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/** ARM Cortex-A15. */
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cpuinfo_uarch_cortex_a15 = 0x00300215,
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/** ARM Cortex-A17. */
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cpuinfo_uarch_cortex_a17 = 0x00300217,
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/** ARM Cortex-A32. */
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cpuinfo_uarch_cortex_a32 = 0x00300332,
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/** ARM Cortex-A35. */
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cpuinfo_uarch_cortex_a35 = 0x00300335,
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/** ARM Cortex-A53. */
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cpuinfo_uarch_cortex_a53 = 0x00300353,
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/** ARM Cortex-A55 revision 0 (restricted dual-issue capabilities compared to revision 1+). */
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cpuinfo_uarch_cortex_a55r0 = 0x00300354,
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/** ARM Cortex-A55. */
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cpuinfo_uarch_cortex_a55 = 0x00300355,
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/** ARM Cortex-A57. */
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cpuinfo_uarch_cortex_a57 = 0x00300357,
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/** ARM Cortex-A65. */
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cpuinfo_uarch_cortex_a65 = 0x00300365,
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/** ARM Cortex-A72. */
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cpuinfo_uarch_cortex_a72 = 0x00300372,
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/** ARM Cortex-A73. */
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cpuinfo_uarch_cortex_a73 = 0x00300373,
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/** ARM Cortex-A75. */
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cpuinfo_uarch_cortex_a75 = 0x00300375,
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/** ARM Cortex-A76. */
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cpuinfo_uarch_cortex_a76 = 0x00300376,
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/** ARM Cortex-A77. */
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cpuinfo_uarch_cortex_a77 = 0x00300377,
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/** ARM Cortex-A78. */
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cpuinfo_uarch_cortex_a78 = 0x00300378,
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/** ARM Neoverse N1. */
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cpuinfo_uarch_neoverse_n1 = 0x00300400,
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/** ARM Neoverse E1. */
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cpuinfo_uarch_neoverse_e1 = 0x00300401,
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/** ARM Neoverse V1. */
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cpuinfo_uarch_neoverse_v1 = 0x00300402,
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/** ARM Neoverse N2. */
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cpuinfo_uarch_neoverse_n2 = 0x00300403,
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/** ARM Neoverse V2. */
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cpuinfo_uarch_neoverse_v2 = 0x00300404,
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/** ARM Cortex-X1. */
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cpuinfo_uarch_cortex_x1 = 0x00300501,
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/** ARM Cortex-X2. */
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cpuinfo_uarch_cortex_x2 = 0x00300502,
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/** ARM Cortex-X3. */
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cpuinfo_uarch_cortex_x3 = 0x00300503,
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/** ARM Cortex-A510. */
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cpuinfo_uarch_cortex_a510 = 0x00300551,
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/** ARM Cortex-A710. */
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cpuinfo_uarch_cortex_a710 = 0x00300571,
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/** ARM Cortex-A715. */
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cpuinfo_uarch_cortex_a715 = 0x00300572,
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/** Qualcomm Scorpion. */
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cpuinfo_uarch_scorpion = 0x00400100,
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/** Qualcomm Krait. */
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cpuinfo_uarch_krait = 0x00400101,
|
|
/** Qualcomm Kryo. */
|
|
cpuinfo_uarch_kryo = 0x00400102,
|
|
/** Qualcomm Falkor. */
|
|
cpuinfo_uarch_falkor = 0x00400103,
|
|
/** Qualcomm Saphira. */
|
|
cpuinfo_uarch_saphira = 0x00400104,
|
|
|
|
/** Nvidia Denver. */
|
|
cpuinfo_uarch_denver = 0x00500100,
|
|
/** Nvidia Denver 2. */
|
|
cpuinfo_uarch_denver2 = 0x00500101,
|
|
/** Nvidia Carmel. */
|
|
cpuinfo_uarch_carmel = 0x00500102,
|
|
|
|
/** Samsung Exynos M1 (Exynos 8890 big cores). */
|
|
cpuinfo_uarch_exynos_m1 = 0x00600100,
|
|
/** Samsung Exynos M2 (Exynos 8895 big cores). */
|
|
cpuinfo_uarch_exynos_m2 = 0x00600101,
|
|
/** Samsung Exynos M3 (Exynos 9810 big cores). */
|
|
cpuinfo_uarch_exynos_m3 = 0x00600102,
|
|
/** Samsung Exynos M4 (Exynos 9820 big cores). */
|
|
cpuinfo_uarch_exynos_m4 = 0x00600103,
|
|
/** Samsung Exynos M5 (Exynos 9830 big cores). */
|
|
cpuinfo_uarch_exynos_m5 = 0x00600104,
|
|
|
|
/* Deprecated synonym for Cortex-A76 */
|
|
cpuinfo_uarch_cortex_a76ae = 0x00300376,
|
|
/* Deprecated names for Exynos. */
|
|
cpuinfo_uarch_mongoose_m1 = 0x00600100,
|
|
cpuinfo_uarch_mongoose_m2 = 0x00600101,
|
|
cpuinfo_uarch_meerkat_m3 = 0x00600102,
|
|
cpuinfo_uarch_meerkat_m4 = 0x00600103,
|
|
|
|
/** Apple A6 and A6X processors. */
|
|
cpuinfo_uarch_swift = 0x00700100,
|
|
/** Apple A7 processor. */
|
|
cpuinfo_uarch_cyclone = 0x00700101,
|
|
/** Apple A8 and A8X processor. */
|
|
cpuinfo_uarch_typhoon = 0x00700102,
|
|
/** Apple A9 and A9X processor. */
|
|
cpuinfo_uarch_twister = 0x00700103,
|
|
/** Apple A10 and A10X processor. */
|
|
cpuinfo_uarch_hurricane = 0x00700104,
|
|
/** Apple A11 processor (big cores). */
|
|
cpuinfo_uarch_monsoon = 0x00700105,
|
|
/** Apple A11 processor (little cores). */
|
|
cpuinfo_uarch_mistral = 0x00700106,
|
|
/** Apple A12 processor (big cores). */
|
|
cpuinfo_uarch_vortex = 0x00700107,
|
|
/** Apple A12 processor (little cores). */
|
|
cpuinfo_uarch_tempest = 0x00700108,
|
|
/** Apple A13 processor (big cores). */
|
|
cpuinfo_uarch_lightning = 0x00700109,
|
|
/** Apple A13 processor (little cores). */
|
|
cpuinfo_uarch_thunder = 0x0070010A,
|
|
/** Apple A14 / M1 processor (big cores). */
|
|
cpuinfo_uarch_firestorm = 0x0070010B,
|
|
/** Apple A14 / M1 processor (little cores). */
|
|
cpuinfo_uarch_icestorm = 0x0070010C,
|
|
/** Apple A15 / M2 processor (big cores). */
|
|
cpuinfo_uarch_avalanche = 0x0070010D,
|
|
/** Apple A15 / M2 processor (little cores). */
|
|
cpuinfo_uarch_blizzard = 0x0070010E,
|
|
|
|
/** Cavium ThunderX. */
|
|
cpuinfo_uarch_thunderx = 0x00800100,
|
|
/** Cavium ThunderX2 (originally Broadcom Vulkan). */
|
|
cpuinfo_uarch_thunderx2 = 0x00800200,
|
|
|
|
/** Marvell PJ4. */
|
|
cpuinfo_uarch_pj4 = 0x00900100,
|
|
|
|
/** Broadcom Brahma B15. */
|
|
cpuinfo_uarch_brahma_b15 = 0x00A00100,
|
|
/** Broadcom Brahma B53. */
|
|
cpuinfo_uarch_brahma_b53 = 0x00A00101,
|
|
|
|
/** Applied Micro X-Gene. */
|
|
cpuinfo_uarch_xgene = 0x00B00100,
|
|
|
|
/* Hygon Dhyana (a modification of AMD Zen for Chinese market). */
|
|
cpuinfo_uarch_dhyana = 0x01000100,
|
|
|
|
/** HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors). */
|
|
cpuinfo_uarch_taishan_v110 = 0x00C00100,
|
|
};
|
|
|
|
struct cpuinfo_processor {
|
|
/** SMT (hyperthread) ID within a core */
|
|
uint32_t smt_id;
|
|
/** Core containing this logical processor */
|
|
const struct cpuinfo_core* core;
|
|
/** Cluster of cores containing this logical processor */
|
|
const struct cpuinfo_cluster* cluster;
|
|
/** Physical package containing this logical processor */
|
|
const struct cpuinfo_package* package;
|
|
#if defined(__linux__)
|
|
/**
|
|
* Linux-specific ID for the logical processor:
|
|
* - Linux kernel exposes information about this logical processor in /sys/devices/system/cpu/cpu<linux_id>/
|
|
* - Bit <linux_id> in the cpu_set_t identifies this logical processor
|
|
*/
|
|
int linux_id;
|
|
#endif
|
|
#if defined(_WIN32) || defined(__CYGWIN__)
|
|
/** Windows-specific ID for the group containing the logical processor. */
|
|
uint16_t windows_group_id;
|
|
/**
|
|
* Windows-specific ID of the logical processor within its group:
|
|
* - Bit <windows_processor_id> in the KAFFINITY mask identifies this logical processor within its group.
|
|
*/
|
|
uint16_t windows_processor_id;
|
|
#endif
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
/** APIC ID (unique x86-specific ID of the logical processor) */
|
|
uint32_t apic_id;
|
|
#endif
|
|
struct {
|
|
/** Level 1 instruction cache */
|
|
const struct cpuinfo_cache* l1i;
|
|
/** Level 1 data cache */
|
|
const struct cpuinfo_cache* l1d;
|
|
/** Level 2 unified or data cache */
|
|
const struct cpuinfo_cache* l2;
|
|
/** Level 3 unified or data cache */
|
|
const struct cpuinfo_cache* l3;
|
|
/** Level 4 unified or data cache */
|
|
const struct cpuinfo_cache* l4;
|
|
} cache;
|
|
};
|
|
|
|
struct cpuinfo_core {
|
|
/** Index of the first logical processor on this core. */
|
|
uint32_t processor_start;
|
|
/** Number of logical processors on this core */
|
|
uint32_t processor_count;
|
|
/** Core ID within a package */
|
|
uint32_t core_id;
|
|
/** Cluster containing this core */
|
|
const struct cpuinfo_cluster* cluster;
|
|
/** Physical package containing this core. */
|
|
const struct cpuinfo_package* package;
|
|
/** Vendor of the CPU microarchitecture for this core */
|
|
enum cpuinfo_vendor vendor;
|
|
/** CPU microarchitecture for this core */
|
|
enum cpuinfo_uarch uarch;
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
/** Value of CPUID leaf 1 EAX register for this core */
|
|
uint32_t cpuid;
|
|
#elif CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
|
|
/** Value of Main ID Register (MIDR) for this core */
|
|
uint32_t midr;
|
|
#endif
|
|
/** Clock rate (non-Turbo) of the core, in Hz */
|
|
uint64_t frequency;
|
|
};
|
|
|
|
struct cpuinfo_cluster {
|
|
/** Index of the first logical processor in the cluster */
|
|
uint32_t processor_start;
|
|
/** Number of logical processors in the cluster */
|
|
uint32_t processor_count;
|
|
/** Index of the first core in the cluster */
|
|
uint32_t core_start;
|
|
/** Number of cores on the cluster */
|
|
uint32_t core_count;
|
|
/** Cluster ID within a package */
|
|
uint32_t cluster_id;
|
|
/** Physical package containing the cluster */
|
|
const struct cpuinfo_package* package;
|
|
/** CPU microarchitecture vendor of the cores in the cluster */
|
|
enum cpuinfo_vendor vendor;
|
|
/** CPU microarchitecture of the cores in the cluster */
|
|
enum cpuinfo_uarch uarch;
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
/** Value of CPUID leaf 1 EAX register of the cores in the cluster */
|
|
uint32_t cpuid;
|
|
#elif CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
|
|
/** Value of Main ID Register (MIDR) of the cores in the cluster */
|
|
uint32_t midr;
|
|
#endif
|
|
/** Clock rate (non-Turbo) of the cores in the cluster, in Hz */
|
|
uint64_t frequency;
|
|
};
|
|
|
|
#define CPUINFO_PACKAGE_NAME_MAX 48
|
|
|
|
struct cpuinfo_package {
|
|
/** SoC or processor chip model name */
|
|
char name[CPUINFO_PACKAGE_NAME_MAX];
|
|
/** Index of the first logical processor on this physical package */
|
|
uint32_t processor_start;
|
|
/** Number of logical processors on this physical package */
|
|
uint32_t processor_count;
|
|
/** Index of the first core on this physical package */
|
|
uint32_t core_start;
|
|
/** Number of cores on this physical package */
|
|
uint32_t core_count;
|
|
/** Index of the first cluster of cores on this physical package */
|
|
uint32_t cluster_start;
|
|
/** Number of clusters of cores on this physical package */
|
|
uint32_t cluster_count;
|
|
};
|
|
|
|
struct cpuinfo_uarch_info {
|
|
/** Type of CPU microarchitecture */
|
|
enum cpuinfo_uarch uarch;
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
/** Value of CPUID leaf 1 EAX register for the microarchitecture */
|
|
uint32_t cpuid;
|
|
#elif CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
|
|
/** Value of Main ID Register (MIDR) for the microarchitecture */
|
|
uint32_t midr;
|
|
#endif
|
|
/** Number of logical processors with the microarchitecture */
|
|
uint32_t processor_count;
|
|
/** Number of cores with the microarchitecture */
|
|
uint32_t core_count;
|
|
};
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
bool CPUINFO_ABI cpuinfo_initialize(void);
|
|
|
|
void CPUINFO_ABI cpuinfo_deinitialize(void);
|
|
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
/* This structure is not a part of stable API. Use cpuinfo_has_x86_* functions instead. */
|
|
struct cpuinfo_x86_isa {
|
|
#if CPUINFO_ARCH_X86
|
|
bool rdtsc;
|
|
#endif
|
|
bool rdtscp;
|
|
bool rdpid;
|
|
bool sysenter;
|
|
#if CPUINFO_ARCH_X86
|
|
bool syscall;
|
|
#endif
|
|
bool msr;
|
|
bool clzero;
|
|
bool clflush;
|
|
bool clflushopt;
|
|
bool mwait;
|
|
bool mwaitx;
|
|
#if CPUINFO_ARCH_X86
|
|
bool emmx;
|
|
#endif
|
|
bool fxsave;
|
|
bool xsave;
|
|
#if CPUINFO_ARCH_X86
|
|
bool fpu;
|
|
bool mmx;
|
|
bool mmx_plus;
|
|
#endif
|
|
bool three_d_now;
|
|
bool three_d_now_plus;
|
|
#if CPUINFO_ARCH_X86
|
|
bool three_d_now_geode;
|
|
#endif
|
|
bool prefetch;
|
|
bool prefetchw;
|
|
bool prefetchwt1;
|
|
#if CPUINFO_ARCH_X86
|
|
bool daz;
|
|
bool sse;
|
|
bool sse2;
|
|
#endif
|
|
bool sse3;
|
|
bool ssse3;
|
|
bool sse4_1;
|
|
bool sse4_2;
|
|
bool sse4a;
|
|
bool misaligned_sse;
|
|
bool avx;
|
|
bool avxvnni;
|
|
bool fma3;
|
|
bool fma4;
|
|
bool xop;
|
|
bool f16c;
|
|
bool avx2;
|
|
bool avx512f;
|
|
bool avx512pf;
|
|
bool avx512er;
|
|
bool avx512cd;
|
|
bool avx512dq;
|
|
bool avx512bw;
|
|
bool avx512vl;
|
|
bool avx512ifma;
|
|
bool avx512vbmi;
|
|
bool avx512vbmi2;
|
|
bool avx512bitalg;
|
|
bool avx512vpopcntdq;
|
|
bool avx512vnni;
|
|
bool avx512bf16;
|
|
bool avx512fp16;
|
|
bool avx512vp2intersect;
|
|
bool avx512_4vnniw;
|
|
bool avx512_4fmaps;
|
|
bool hle;
|
|
bool rtm;
|
|
bool xtest;
|
|
bool mpx;
|
|
#if CPUINFO_ARCH_X86
|
|
bool cmov;
|
|
bool cmpxchg8b;
|
|
#endif
|
|
bool cmpxchg16b;
|
|
bool clwb;
|
|
bool movbe;
|
|
#if CPUINFO_ARCH_X86_64
|
|
bool lahf_sahf;
|
|
#endif
|
|
bool fs_gs_base;
|
|
bool lzcnt;
|
|
bool popcnt;
|
|
bool tbm;
|
|
bool bmi;
|
|
bool bmi2;
|
|
bool adx;
|
|
bool aes;
|
|
bool vaes;
|
|
bool pclmulqdq;
|
|
bool vpclmulqdq;
|
|
bool gfni;
|
|
bool rdrand;
|
|
bool rdseed;
|
|
bool sha;
|
|
bool rng;
|
|
bool ace;
|
|
bool ace2;
|
|
bool phe;
|
|
bool pmm;
|
|
bool lwp;
|
|
};
|
|
|
|
extern struct cpuinfo_x86_isa cpuinfo_isa;
|
|
#endif
|
|
|
|
static inline bool cpuinfo_has_x86_rdtsc(void) {
|
|
#if CPUINFO_ARCH_X86_64
|
|
return true;
|
|
#elif CPUINFO_ARCH_X86
|
|
#if defined(__ANDROID__)
|
|
return true;
|
|
#else
|
|
return cpuinfo_isa.rdtsc;
|
|
#endif
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_rdtscp(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.rdtscp;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_rdpid(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.rdpid;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_clzero(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.clzero;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_mwait(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.mwait;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_mwaitx(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.mwaitx;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_fxsave(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.fxsave;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_xsave(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.xsave;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_fpu(void) {
|
|
#if CPUINFO_ARCH_X86_64
|
|
return true;
|
|
#elif CPUINFO_ARCH_X86
|
|
#if defined(__ANDROID__)
|
|
return true;
|
|
#else
|
|
return cpuinfo_isa.fpu;
|
|
#endif
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_mmx(void) {
|
|
#if CPUINFO_ARCH_X86_64
|
|
return true;
|
|
#elif CPUINFO_ARCH_X86
|
|
#if defined(__ANDROID__)
|
|
return true;
|
|
#else
|
|
return cpuinfo_isa.mmx;
|
|
#endif
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_mmx_plus(void) {
|
|
#if CPUINFO_ARCH_X86_64
|
|
return true;
|
|
#elif CPUINFO_ARCH_X86
|
|
#if defined(__ANDROID__)
|
|
return true;
|
|
#else
|
|
return cpuinfo_isa.mmx_plus;
|
|
#endif
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_3dnow(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.three_d_now;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_3dnow_plus(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.three_d_now_plus;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_3dnow_geode(void) {
|
|
#if CPUINFO_ARCH_X86_64
|
|
return false;
|
|
#elif CPUINFO_ARCH_X86
|
|
#if defined(__ANDROID__)
|
|
return false;
|
|
#else
|
|
return cpuinfo_isa.three_d_now_geode;
|
|
#endif
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_prefetch(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.prefetch;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_prefetchw(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.prefetchw;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_prefetchwt1(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.prefetchwt1;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_daz(void) {
|
|
#if CPUINFO_ARCH_X86_64
|
|
return true;
|
|
#elif CPUINFO_ARCH_X86
|
|
#if defined(__ANDROID__)
|
|
return true;
|
|
#else
|
|
return cpuinfo_isa.daz;
|
|
#endif
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_sse(void) {
|
|
#if CPUINFO_ARCH_X86_64
|
|
return true;
|
|
#elif CPUINFO_ARCH_X86
|
|
#if defined(__ANDROID__)
|
|
return true;
|
|
#else
|
|
return cpuinfo_isa.sse;
|
|
#endif
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_sse2(void) {
|
|
#if CPUINFO_ARCH_X86_64
|
|
return true;
|
|
#elif CPUINFO_ARCH_X86
|
|
#if defined(__ANDROID__)
|
|
return true;
|
|
#else
|
|
return cpuinfo_isa.sse2;
|
|
#endif
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_sse3(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
#if defined(__ANDROID__)
|
|
return true;
|
|
#else
|
|
return cpuinfo_isa.sse3;
|
|
#endif
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_ssse3(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
#if defined(__ANDROID__)
|
|
return true;
|
|
#else
|
|
return cpuinfo_isa.ssse3;
|
|
#endif
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_sse4_1(void) {
|
|
#if CPUINFO_ARCH_X86_64
|
|
#if defined(__ANDROID__)
|
|
return true;
|
|
#else
|
|
return cpuinfo_isa.sse4_1;
|
|
#endif
|
|
#elif CPUINFO_ARCH_X86
|
|
return cpuinfo_isa.sse4_1;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_sse4_2(void) {
|
|
#if CPUINFO_ARCH_X86_64
|
|
#if defined(__ANDROID__)
|
|
return true;
|
|
#else
|
|
return cpuinfo_isa.sse4_2;
|
|
#endif
|
|
#elif CPUINFO_ARCH_X86
|
|
return cpuinfo_isa.sse4_2;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_sse4a(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.sse4a;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_misaligned_sse(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.misaligned_sse;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avxvnni(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avxvnni;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_fma3(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.fma3;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_fma4(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.fma4;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_xop(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.xop;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_f16c(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.f16c;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx2(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx2;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx512f(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx512f;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx512pf(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx512pf;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx512er(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx512er;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx512cd(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx512cd;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx512dq(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx512dq;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx512bw(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx512bw;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx512vl(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx512vl;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx512ifma(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx512ifma;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx512vbmi(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx512vbmi;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx512vbmi2(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx512vbmi2;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx512bitalg(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx512bitalg;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx512vpopcntdq(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx512vpopcntdq;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx512vnni(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx512vnni;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx512bf16(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx512bf16;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx512fp16(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx512fp16;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx512vp2intersect(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx512vp2intersect;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx512_4vnniw(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx512_4vnniw;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_avx512_4fmaps(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.avx512_4fmaps;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_hle(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.hle;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_rtm(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.rtm;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_xtest(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.xtest;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_mpx(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.mpx;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_cmov(void) {
|
|
#if CPUINFO_ARCH_X86_64
|
|
return true;
|
|
#elif CPUINFO_ARCH_X86
|
|
return cpuinfo_isa.cmov;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_cmpxchg8b(void) {
|
|
#if CPUINFO_ARCH_X86_64
|
|
return true;
|
|
#elif CPUINFO_ARCH_X86
|
|
return cpuinfo_isa.cmpxchg8b;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_cmpxchg16b(void) {
|
|
#if CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.cmpxchg16b;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_clwb(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.clwb;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_movbe(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.movbe;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_lahf_sahf(void) {
|
|
#if CPUINFO_ARCH_X86
|
|
return true;
|
|
#elif CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.lahf_sahf;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_lzcnt(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.lzcnt;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_popcnt(void) {
|
|
#if CPUINFO_ARCH_X86_64
|
|
#if defined(__ANDROID__)
|
|
return true;
|
|
#else
|
|
return cpuinfo_isa.popcnt;
|
|
#endif
|
|
#elif CPUINFO_ARCH_X86
|
|
return cpuinfo_isa.popcnt;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_tbm(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.tbm;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_bmi(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.bmi;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_bmi2(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.bmi2;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_adx(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.adx;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_aes(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.aes;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_vaes(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.vaes;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_pclmulqdq(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.pclmulqdq;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_vpclmulqdq(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.vpclmulqdq;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_gfni(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.gfni;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_rdrand(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.rdrand;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_rdseed(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.rdseed;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_x86_sha(void) {
|
|
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
|
|
return cpuinfo_isa.sha;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
|
|
/* This structure is not a part of stable API. Use cpuinfo_has_arm_* functions instead. */
|
|
struct cpuinfo_arm_isa {
|
|
#if CPUINFO_ARCH_ARM
|
|
bool thumb;
|
|
bool thumb2;
|
|
bool thumbee;
|
|
bool jazelle;
|
|
bool armv5e;
|
|
bool armv6;
|
|
bool armv6k;
|
|
bool armv7;
|
|
bool armv7mp;
|
|
bool armv8;
|
|
bool idiv;
|
|
|
|
bool vfpv2;
|
|
bool vfpv3;
|
|
bool d32;
|
|
bool fp16;
|
|
bool fma;
|
|
|
|
bool wmmx;
|
|
bool wmmx2;
|
|
bool neon;
|
|
#endif
|
|
#if CPUINFO_ARCH_ARM64
|
|
bool atomics;
|
|
bool bf16;
|
|
bool sve;
|
|
bool sve2;
|
|
bool i8mm;
|
|
#endif
|
|
bool rdm;
|
|
bool fp16arith;
|
|
bool dot;
|
|
bool jscvt;
|
|
bool fcma;
|
|
bool fhm;
|
|
|
|
bool aes;
|
|
bool sha1;
|
|
bool sha2;
|
|
bool pmull;
|
|
bool crc32;
|
|
};
|
|
|
|
extern struct cpuinfo_arm_isa cpuinfo_isa;
|
|
#endif
|
|
|
|
static inline bool cpuinfo_has_arm_thumb(void) {
|
|
#if CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.thumb;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_thumb2(void) {
|
|
#if CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.thumb2;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_v5e(void) {
|
|
#if CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.armv5e;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_v6(void) {
|
|
#if CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.armv6;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_v6k(void) {
|
|
#if CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.armv6k;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_v7(void) {
|
|
#if CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.armv7;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_v7mp(void) {
|
|
#if CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.armv7mp;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_v8(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return true;
|
|
#elif CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.armv8;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_idiv(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return true;
|
|
#elif CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.idiv;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_vfpv2(void) {
|
|
#if CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.vfpv2;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_vfpv3(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return true;
|
|
#elif CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.vfpv3;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_vfpv3_d32(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return true;
|
|
#elif CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.vfpv3 && cpuinfo_isa.d32;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_vfpv3_fp16(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return true;
|
|
#elif CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.vfpv3 && cpuinfo_isa.fp16;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_vfpv3_fp16_d32(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return true;
|
|
#elif CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.vfpv3 && cpuinfo_isa.fp16 && cpuinfo_isa.d32;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_vfpv4(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return true;
|
|
#elif CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.vfpv3 && cpuinfo_isa.fma;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_vfpv4_d32(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return true;
|
|
#elif CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.vfpv3 && cpuinfo_isa.fma && cpuinfo_isa.d32;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_fp16_arith(void) {
|
|
#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.fp16arith;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_bf16(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.bf16;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_wmmx(void) {
|
|
#if CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.wmmx;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_wmmx2(void) {
|
|
#if CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.wmmx2;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_neon(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return true;
|
|
#elif CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.neon;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_neon_fp16(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return true;
|
|
#elif CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.neon && cpuinfo_isa.fp16;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_neon_fma(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return true;
|
|
#elif CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.neon && cpuinfo_isa.fma;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_neon_v8(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return true;
|
|
#elif CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.neon && cpuinfo_isa.armv8;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_atomics(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.atomics;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_neon_rdm(void) {
|
|
#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.rdm;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_neon_fp16_arith(void) {
|
|
#if CPUINFO_ARCH_ARM
|
|
return cpuinfo_isa.neon && cpuinfo_isa.fp16arith;
|
|
#elif CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.fp16arith;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_fhm(void) {
|
|
#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.fhm;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_neon_dot(void) {
|
|
#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.dot;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_neon_bf16(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.bf16;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_jscvt(void) {
|
|
#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.jscvt;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_fcma(void) {
|
|
#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.fcma;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_i8mm(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.i8mm;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_aes(void) {
|
|
#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.aes;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_sha1(void) {
|
|
#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.sha1;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_sha2(void) {
|
|
#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.sha2;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_pmull(void) {
|
|
#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.pmull;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_crc32(void) {
|
|
#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.crc32;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_sve(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.sve;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_sve_bf16(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.sve && cpuinfo_isa.bf16;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
static inline bool cpuinfo_has_arm_sve2(void) {
|
|
#if CPUINFO_ARCH_ARM64
|
|
return cpuinfo_isa.sve2;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_processors(void);
|
|
const struct cpuinfo_core* CPUINFO_ABI cpuinfo_get_cores(void);
|
|
const struct cpuinfo_cluster* CPUINFO_ABI cpuinfo_get_clusters(void);
|
|
const struct cpuinfo_package* CPUINFO_ABI cpuinfo_get_packages(void);
|
|
const struct cpuinfo_uarch_info* CPUINFO_ABI cpuinfo_get_uarchs(void);
|
|
const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1i_caches(void);
|
|
const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1d_caches(void);
|
|
const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l2_caches(void);
|
|
const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l3_caches(void);
|
|
const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l4_caches(void);
|
|
|
|
const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_processor(uint32_t index);
|
|
const struct cpuinfo_core* CPUINFO_ABI cpuinfo_get_core(uint32_t index);
|
|
const struct cpuinfo_cluster* CPUINFO_ABI cpuinfo_get_cluster(uint32_t index);
|
|
const struct cpuinfo_package* CPUINFO_ABI cpuinfo_get_package(uint32_t index);
|
|
const struct cpuinfo_uarch_info* CPUINFO_ABI cpuinfo_get_uarch(uint32_t index);
|
|
const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1i_cache(uint32_t index);
|
|
const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1d_cache(uint32_t index);
|
|
const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l2_cache(uint32_t index);
|
|
const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l3_cache(uint32_t index);
|
|
const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l4_cache(uint32_t index);
|
|
|
|
uint32_t CPUINFO_ABI cpuinfo_get_processors_count(void);
|
|
uint32_t CPUINFO_ABI cpuinfo_get_cores_count(void);
|
|
uint32_t CPUINFO_ABI cpuinfo_get_clusters_count(void);
|
|
uint32_t CPUINFO_ABI cpuinfo_get_packages_count(void);
|
|
uint32_t CPUINFO_ABI cpuinfo_get_uarchs_count(void);
|
|
uint32_t CPUINFO_ABI cpuinfo_get_l1i_caches_count(void);
|
|
uint32_t CPUINFO_ABI cpuinfo_get_l1d_caches_count(void);
|
|
uint32_t CPUINFO_ABI cpuinfo_get_l2_caches_count(void);
|
|
uint32_t CPUINFO_ABI cpuinfo_get_l3_caches_count(void);
|
|
uint32_t CPUINFO_ABI cpuinfo_get_l4_caches_count(void);
|
|
|
|
/**
|
|
* Returns upper bound on cache size.
|
|
*/
|
|
uint32_t CPUINFO_ABI cpuinfo_get_max_cache_size(void);
|
|
|
|
/**
|
|
* Identify the logical processor that executes the current thread.
|
|
*
|
|
* There is no guarantee that the thread will stay on the same logical processor for any time.
|
|
* Callers should treat the result as only a hint, and be prepared to handle NULL return value.
|
|
*/
|
|
const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_current_processor(void);
|
|
|
|
/**
|
|
* Identify the core that executes the current thread.
|
|
*
|
|
* There is no guarantee that the thread will stay on the same core for any time.
|
|
* Callers should treat the result as only a hint, and be prepared to handle NULL return value.
|
|
*/
|
|
const struct cpuinfo_core* CPUINFO_ABI cpuinfo_get_current_core(void);
|
|
|
|
/**
|
|
* Identify the microarchitecture index of the core that executes the current thread.
|
|
* If the system does not support such identification, the function returns 0.
|
|
*
|
|
* There is no guarantee that the thread will stay on the same type of core for any time.
|
|
* Callers should treat the result as only a hint.
|
|
*/
|
|
uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index(void);
|
|
|
|
/**
|
|
* Identify the microarchitecture index of the core that executes the current thread.
|
|
* If the system does not support such identification, the function returns the user-specified default value.
|
|
*
|
|
* There is no guarantee that the thread will stay on the same type of core for any time.
|
|
* Callers should treat the result as only a hint.
|
|
*/
|
|
uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index_with_default(uint32_t default_uarch_index);
|
|
|
|
#ifdef __cplusplus
|
|
} /* extern "C" */
|
|
#endif
|
|
|
|
#endif /* CPUINFO_H */
|